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SONY(R)
Description
CXK77B1840GB
4A/4/45A/45
4Mb Late Write HSTL High Speed Synchronous SRAM (256K x 18 Organization)
The CXK77B1840 is a high speed BiCMOS synchronous static RAM with common I/O pins, organized as 262,144-words by 18-bits. This synchronous SRAM integrates input registers, high speed RAM, output registers/latches, and a one-deep write buffer onto a single monolithic IC. Four different read protocols - Register-Register (R-R), Register-Latch (R-L), Register-Flow Thru (R-FT), and Dual Clock (DC), and an enhanced write protocol - Late (Delayed) Write (LW), are supported, providing a flexible, high-performance user interface. All input signals except G (Output Enable) and ZZ (Sleep Mode) are registered on the positive edge of K clock. Read cycles can be controlled in one of four ways - with registered outputs in Register-Register mode, with latched outputs in Register-Latch mode, with flow-through outputs in Register-Flow Thru mode, or with registered outputs using a dedicated output control clock (C clock) in Dual Clock mode. The read protocol is user-selectable through external mode pins M1 and M2. Write cycles follow a Late Write protocol, where data is provided to the SRAM one clock cycle after the address and control signals, eliminating one dead cycle from Read-to-Write transitions. In this scheme, when a write cycle is initiated, the address and data stored in the SRAM's write buffer during the previous write cycle are directed to the SRAM's memory core, while, simultaneously, the address and data from the current write cycle are stored in the SRAM's write buffer. In both Register-Latch and Register-Flow Thru modes, when SW (Global Write Enable) is driven active, the subsequent positive edge of K clock tristates the SRAM's output drivers immediately, allowing consecutive Read-Write-Read operations. The write cycle is internally self-timed, which eliminates complex off-chip write pulse generation and provides increased flexibility for incoming signals. The output drivers are series terminated, and the output impedance is programmable through an external impedance matching resistor RQ. By connecting RQ between ZQ and V SS, the output impedance of all 18 DQ pins can be precisely controlled. Sleep (power down) mode control is provided through the asynchronous ZZ input. 250 MHz operation is obtained from a single 3.3V power supply. JTAG boundary scan interface is provided using a subset of IEEE standard 1149.1 protocol.
Features
R-R Mode R-L, R-FT Modes * Fast Cycle/Access Time tKHKH / tKHQV tKHKH / tKHQV CXK77B1840 -4A 4.0ns / 2.3ns 4.8ns / 4.8ns -4 4.0ns / 2.3ns 5.3ns / 5.3ns -45A 4.0ns / 2.3ns 5.3ns / 5.3ns -45 5.0ns / 2.5ns 6.5ns / 6.5ns Note: Contact Sony Memory Marketing for availability of DC mode functionality. * 4 synchronous modes of operation, selectable by mode pins: Register-Register; Register-Latch; Register-Flow Thru; Dual Clock * Single +3.3V power supply: 3.3V 5% * Dedicated output supply voltage: VDDQ (1.5V typical) * Inputs and outputs are HSTL / extended HSTL compatible. * Differential clock input (K/K, C/C). * All inputs (except asynchronous G and ZZ) and outputs are registered on a single clock edge. * Byte Write capability. * Late Write scheme to eliminate one dead cycle from Read-to-Write transitions. * Self-timed write cycles. * Sleep (power down) mode. * JTAG boundary scan (subset of IEEE standard 1149.1). * 119 pin (7x17) Plastic Ball Grid Array (PBGA) package.
256Kx18, Sync LW, HSTL, rev 4.6 1 / 27 August 20, 1998
**DC Mode** tKHKH / tKHQV 4.0ns / 5.2ns 4.0ns / 5.2ns 4.5ns / 6.0ns 4.5ns / 6.5ns
SONY(R)
CXK77B1840GB Pin Configuration (Top View) 1 A B C D E F G H J K L M N P R T U
VDDQ NC NC DQ0b NC VDDQ NC DQ3b VDDQ NC DQ5b VDDQ DQ7b NC NC NC VDDQ
2
SA6 NC SA12 NC DQ1b NC DQ2b NC VDD DQ4b NC DQ6b NC DQ8b SA10 SA17 TMS
3
SA7 SA8 SA5 VSS VSS VSS SBWb VSS VREF VSS VSS VSS VSS VSS M1 SA9 TDI
4
NC NC VDD ZQ SS G C C VDD K K SW SA14 SA11 VDD NC TCK
5
SA3 SA4 SA0 VSS VSS VSS VSS VSS VREF VSS SBWa VSS VSS VSS M2 SA1 TDO
6
SA2 NC SA13 DQ8a NC DQ6a NC DQ4a VDD NC DQ2a NC DQ1a NC SA15 SA16 NC
7
VDDQ NC NC NC DQ7a VDDQ DQ5a NC VDDQ DQ3a NC VDDQ NC DQ0a NC ZZ VDDQ
Pin Description
Symbol SA DQ K,K C,C SW SBWx SS Description Address Input (0-17) Data I/O (0-8), Bytes a,b Differential Input Clocks Differential Output Control Clocks Write Enable, Global Write Enable, Bytes a,b Synchronous Select Symbol G ZZ TCK TMS TDI TDO VDD Description Async. Output Enable Async. Sleep Mode JTAG Clock (LVTTL) JTAG Mode Select (LVTTL) JTAG Data In (LVTTL) JTAG Data Out (LVTTL) +3.3V Power Supply Symbol V DDQ VSS VREF ZQ M1,M2 NC Description Output Power Supply Ground Input Reference Voltage Output Impedance Control Resistor Input Mode Select No Connect
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SONY(R)
CXK77B1840GB
BLOCK DIAGRAM
18 Input Reg. SA 0-17 Kint 2:1 Mux Write Store Reg.
Add. Dout 256K x 18 Write pulse Reg. Read Comp. Din 2:1 Mux
Output
^
latch
DQ
SS
Reg. Kint
^
SW
Reg. Kint 4
^ ^
Self Time Write Logic
SBW a-d
Reg. Kint
Input Clock 2 K/K C/C 2 M1 M2 Mode Control Output Clock
Kint
G
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CXK77B1840GB
*Truth Tables
Register - Register Mode
ZZ H L L L L L L SS (tn) X H L L L L L SW (tn) X X H H L L L SBWx (tn) X X X X L X H G X X H L X X X Mode Sleep Mode. Power Down Deselect Read Read Write All Bytes (Bits 0-17) Write Bytes With SBWx=L Abort Write DQ0-17 (tn) Hi - Z X Hi - Z X X X X DQ0-17 (tn+1) Hi - Z Hi - Z Hi - Z Q(tn) D(tn) D(tn) Hi - Z VDD Current ISB IDD IDD IDD IDD IDD IDD
Register - Latch and Register - Flow Thru Mode
ZZ H L L L L L L SS (tn) X H L L L L L SW (tn) X X H H L L L SBWx (tn) X X X X L X H G X X H L X X X Mode Sleep Mode. Power Down Deselect Read Read Write All Bytes (Bits 0-17) Write Bytes With SBWx=L Abort Write DQ0-17 (tn) Hi - Z Hi - Z Hi - Z Q(tn) Hi - Z Hi - Z Hi - Z DQ0-17 (tn+1) Hi - Z X Hi - Z X D(tn) D(tn) X VDD Current ISB IDD IDD IDD IDD IDD IDD
Dual Clock Mode
ZZ H L L L L L L SS (tn) X H L L L L L SW (tn) X X H H L L L SBWx (tn) X X X X L X H G X X H L X X X Mode Sleep Mode. Power Down Deselect Read Read Write All Bytes (Bits 0-17) Write Bytes With SBWx=L Abort Write DQ0-17 (tn) Hi - Z Hi - Z Hi - Z Q(tn) Hi - Z Hi - Z Hi - Z DQ0-17 (tn+1) Hi - Z X Hi - Z X D(tn) D(tn) Hi - Z VDD Current ISB IDD IDD IDD IDD IDD IDD
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CXK77B1840GB
*Mode Select
This device supports four different JEDEC standard read protocols via mode pins M1 and M2. The mode pins must be set during power-up and cannot change during SRAM operation. Mode Select Truth Table.
M1 Register-Register Register-Flow Thru Register-Latch Dual Clock L L H H M2 H L L H
*Power-Up Sequence
Power supplies must power up in the following sequence: VSS, VDD, VDDQ, VREF, and Inputs. VDDQ must never exceed VDD.
*Absolute Maximum Ratings(1)
Item Supply Voltage Output Supply Voltage Input Voltage Output Voltage Operating Temperature Junction Temperature Storage Temperature Symbol VDD VDDQ VIN VOUT TA TJ Tstg Rating -0.5 to +4.6 -0.5 to +4.6 -0.5 to VDD+0.5 (4.6V max.) -0.5 to VDDQ+0.5 (4.6V max.) 0 to 70 0 to 110 -55 to 150 Unit V V V V
C C C
(1) Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage
to the device. This is a stress rating only, and functional operation of the device at these or any other conditions other than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
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SONY(R)
CXK77B1840GB (VSS = 0V, TA = 0 to 70oC) Min 3.13 1.4 0.5 VREF + 0.2 -0.3(2) 2.0 -0.3 -0.3 0.4 0.5 0.5 175 Typ 3.3 ----------------0.75 0.75 250 Max 3.47 1.6(3) 1.0 VDDQ + 0.3(1) VREF - 0.2 VDDQ+0.3 0.8 VDDQ+0.3 VDDQ+0.6 1.0 1.0 350 Unit V V V V V V V V V V V
*DC Recommended Operating Conditions.
Item Supply Voltage Output Supply Voltage Input Reference Voltage Input High Voltage Input Low Voltage Input High Voltage - Test Mode Input Low Voltage - Test Mode Clock Input Signal Voltage Clock Input Differential Voltage Clock Input Common Mode Voltage Clock Input Cross Point Voltage Output Impedance Control Resistor
(1) (2) (3)
Symbol VDD VDDQ VREF VIH VIL VTIH VTIL VIN VDIF VCM VX RQ
VIH (Max) AC = V DD+1.5 V for pulse width less than 2.0 ns. VIL (Min) AC = -1.5 V for pulse width less than 2.0 ns. Extended VDDQ support up to 2.0V is available - please contact marketing. (TA = 25oC, f = 1 MHz)
*I/O Capacitance
Item Input Capacitance Clock Input Capacitance Output Capacitance Symbol CIN CCLK COUT Test conditions VIN = 0V VIN = 0V VOUT = 0V Min -------
Max 6 6 7
Unit pF pF pF
Note: These parameters are sampled and are not 100% tested.
*Programmable Impedance Output Drivers
This device has programmable impedance output drivers. The output impedance is controlled by an external resistor, RQ, connected between the SRAM's ZQ pin and VSS, and is equal to one-fifth the value of this resistor. For output impedance matching within a 7.5% tolerance, RQ must be in the range of 175 to 350. For maximum output drive, the ZQ pin can be connected directly to VSS. For minimum output drive, the ZQ pin can be left open or connected to VDDQ. The output impedance is updated whenever the drivers are in a Hi-Z state. At power up, 8192 clock cycles followed by a write or deselect operation are required to ensure that the output impedance has reached its desired value. After power up, periodic updates of the output impedance, via a write or deselect operation, are also required.
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SONY(R)
CXK77B1840GB
(VDD = 3.3V 5%, VSS = 0V, TA = 0 to 70oC)
*DC Electrical Characteristics
Item Input Leakage Current Output Leakage Current Power Supply Operating Current Power Supply Operating Current Power Supply Operating Current Power Supply Operating Current Power Supply Standby Current Output High Voltage Output Low Voltage Output Driver Impedance Symbol ILI ILO IDD4 Test Conditions VIN = VSS to VDD VOUT = VSS to VDD G = VIH Cycle = 6.0ns Duty = 100% IOUT = 0 mA Cycle = 5.0ns Duty = 100% IOUT = 0 mA Cycle = 4.5ns Duty = 100% IOUT = 0 mA Cycle = 4.0ns Duty = 100% IOUT = 0 mA VIH IOH = -6.0 mA RQ=250 IOL = 6.0 mA RQ = 250 VOH = VDDQ/2 VOL = VDDQ/2
Min -1 -10 ---
Typ ----610
Max 1 10 ---
Unit uA uA mA
IDD4
---
650
---
mA
IDD4
---
670
---
mA
IDD4
---
695
---
mA
ISB VOH VOL ROUT1,2,3
--VDDQ-0.4 --(RQ/5)* 0.925
60 ----RQ/5
----0.4 (RQ/5)* 1.075
mA V V
1. RQ needs to be in the range of 175 to 350 for proper control of the value of ROUT. 1.1 ROUT 38 (1.075 * 175/5) when RQ 175 1.2 ROUT 64 (0.925 * 350/5) when RQ 350 2. For maximum output drive, ZQ pin can be tied directly to VSS. The output impedance is as described in note 1.1. 3. For minimum output drive, ZQ pin can be no connect or tied to VDDQ. The output impedance is as described in note 1.2. 4. Typical IDD values measured at VDD = 3.3V and TA = 25oC, with a 75% read / 25% write operation distribution.
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CXK77B1840GB
*AC Electrical Characteristics (Register-Register Mode)
-4A Item Symbol Min Cycle Time Clock High Pulse Width Clock Low Pulse Width Address Setup Time Address Hold Time Write Enables Setup Time Write Enables Hold Time Synchronous Select Setup Time Synchronous Select Hold Time Data Input Setup Time Data Input Hold Time Clock High to Output Valid Clock High to Output Hold Clock High to Output Low-Z Clock High to Output High-Z Output Enable Low to Output Valid Output Enable Low to Output Low-Z Output Enable High to Output High-Z Sleep Mode Enable Time Sleep Mode Recovery Time tKHKH tKHKL tKLKH tAVKH tKHAX tWVKH tKHWX tSVKH tKHSX tDVKH tKHDX tKHQV tKHQX*2 tKHQX1*2 tKHQZ*2 tGLQV tGLQX*2 tGHQZ*2 tZZE*2 tZZR*2 4.0 1.5 1.5 0.5 1.0 0.5 1.0 0.5 1.0 0.5 1.0 --0.7 0.7 ----0.5 ----20.0 Max ----------------------2.3 ----2.3 2.3 --2.3 20.0 --Min 4.0 1.5 1.5 0.5 1.0 0.5 1.0 0.5 1.0 0.5 1.0 --0.7 0.7 ----0.5 ----20.0 Max ----------------------2.3 ----2.3 2.3 --2.3 20.0 --Min 4.0 1.5 1.5 0.5 1.0 0.5 1.0 0.5 1.0 0.5 1.0 --0.7 0.7 ----0.5 ----20.0 Max ----------------------2.3 ----2.3 2.3 --2.3 20.0 --Min 5.0 1.5 1.5 0.5 1.0 0.5 1.0 0.5 1.0 0.5 1.0 --0.7 0.7 ----0.5 ----20.0 Max ----------------------2.5 ----2.5 2.5 --2.3 20.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -4 -45A -45 Unit
1. All parameters are specified over the range TA = 0 to 70oC. 2. These parameters are sampled and are not 100% tested.
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CXK77B1840GB
*AC Electrical Characteristics (Register-Latch & Register-Flow Thru Modes)
-4A Item Symbol Min Cycle Time Clock High Pulse Width Clock Low Pulse Width Address Setup Time Address Hold Time Write Enables Setup Time Write Enables Hold Time Synchronous Select Setup Time Synchronous Select Hold Time Data Input Setup Time Data Input Hold Time Clock High to Output Valid Clock High to Output Hold (R-FT mode only) Clock High to Output Low-Z (R-FT mode only) Clock Low to Output Valid (R-L mode only) Clock Low to Output Hold (R-L mode only) Clock Low to Output Low-Z (R-L mode only) Clock High to Output High-Z Output Enable Low to Output Valid Output Enable Low to Output Low-Z Output Enable High to Output High-Z Sleep Mode Enable Time Sleep Mode Recovery Time tKHKH tKHKL tKLKH tAVKH tKHAX tWVKH tKHWX tSVKH tKHSX tDVKH tKHDX tKHQV tKHQX*2 tKHQX1*2 tKLQV tKLQX*2 tKLQX1*2 tKHQZ*2 tGLQV tGLQX*2 tGHQZ*2 tZZE*2 tZZR*2 4.8 1.5 1.5 0.4*3 0.8*3 0.4*3 0.8*3 0.4*3 0.8*3 0.4*3 0.8*3 --2.0 2.5 --0.7 0.7 ----0.5 ----20.0 Max ----------------------4.8 ----2.2 ----2.2 2.2 --2.2 20.0 --Min 5.3 1.5 1.5 0.5 1.0 0.5 1.0 0.5 1.0 0.5 1.0 --2.0 2.5 --0.7 0.7 ----0.5 ----20.0 Max ----------------------5.3 ----2.3 ----2.3 2.3 --2.3 20.0 --Min 5.3 1.5 1.5 0.5 1.0 0.5 1.0 0.5 1.0 0.5 1.0 --2.0 2.5 --0.7 0.7 ----0.5 ----20.0 Max ----------------------5.3 ----2.5 ----2.5 2.5 --2.3 20.0 --Min 6.5 1.5 1.5 0.5 1.0 0.5 1.0 0.5 1.0 0.5 1.0 --2.0 3.0 --0.7 0.7 ----0.5 ----20.0 Max ----------------------6.5 ----2.5 ----2.5 2.5 --2.3 20.0 --ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -4 -45A -45 Unit
1. All parameters are specified over the range TA = 0 to 70oC. 2. These parameters are sampled and are not 100% tested. 3. For -4A, these parameters are measured from valid VIH/VIL levels to the clock mid-point. 4. R-FT mode operation is verified functionally, but associated timing parameters are guaranteed by design only and are not 100% tested.
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CXK77B1840GB
*AC Electrical Characteristics (Dual Clock Mode)
-4A Item Symbol Min K Clock Cycle Time K Clock High Pulse Width K Clock Low Pulse Width C Clock Cycle Time C Clock High Pulse Width C Clock Low Pulse Width K to C Clock Delay C to K Clock Delay Address Setup Time Address Hold Time Write Enables Setup Time Write Enables Hold Time Synchronous Select Setup Time Synchronous Select Hold Time Data Input Setup Time Data Input Hold Time K Clock High to Output Valid C Clock High to Output Valid C Clock High to Output Hold C Clock High to Output Low-Z C Clock High to Output High-Z Output Enable Low to Output Valid Output Enable Low to Output Low-Z Output Enable High to Output High-Z Sleep Mode Enable Time Sleep Mode Recovery Time tKHKH tKHKL tKLKH tCHCH tCHCL tCLCH tKHCH tCHKH tAVKH tKHAX tWVKH tKHWX tSVKH tKHSX tDVKH tKHDX tKHQV tCHQV tCHQX*2 tCHQX1*2 tCHQZ*2 tGLQV tGLQX*2 tGHQZ*2 tZZE*2 tZZR*2 4.0 1.5 1.5 4.0 1.5 1.5 1.5 0.8 0.5 1.0 0.5 1.0 0.5 1.0 0.5 0.8 ----0.7 0.7 ----0.5 ----20.0 Max --------------------------------5.2 2.3 ----2.3 2.1 --2.0 20.0 --Min 4.0 1.5 1.5 4.0 1.5 1.5 1.5 0.8 0.5 1.0 0.5 1.0 0.5 1.0 0.5 0.8 ----0.7 0.7 ----0.5 ----20.0 Max --------------------------------5.2 2.3 ----2.3 2.1 --2.0 20.0 --Min 4.5 1.5 1.5 4.5 1.5 1.5 1.5 0.8 0.5 1.0 0.5 1.0 0.5 1.0 0.5 1.0 ----0.7 0.7 ----0.5 ----20.0 Max --------------------------------6.0 2.5 ----2.5 2.5 --2.3 20.0 --Min 4.5 1.5 1.5 4.5 1.5 1.5 1.5 0.8 0.5 1.0 0.5 1.0 0.5 1.0 0.5 1.0 ----0.7 0.7 ----0.5 ----20.0 Max --------------------------------6.5 2.5 ----2.5 2.5 --2.3 20.0 --ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -4 -45A -45 Unit
1. All parameters are specified over the range TA = 0 to 70oC. 2. These parameters are sampled and are not 100% tested. 3. Currently, DC mode operation is not verified functionally, and no timing parameters are guaranteed. Contact Sony Memory Marketing for availability.
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CXK77B1840GB
*AC Test Conditions (VDDQ = 1.5V)
(VDD = 3.3V 5%, TA = 0 to 70C)
Item Input Reference Voltage Input High Level Input Low Level Input Rise & Fall Time Clock Input Reference Level Input High Voltage Input Low Voltage Input Rise & Fall Time Output Supply Voltage Output Reference Level Output Load Conditions
Conditions VREF = 0.75V VIH = 1.25V VIL = 0.25V 1V/ns K/K cross; C/C cross 1.25V 0.25V 1V/ns VDDQ = 1.5V 0.75V
Notes
Fig.1 RQ = 250
Fig. 1: AC Test Output Load (VDDQ = 1.5V)
0.75 V 16.7 50 5 pF DQ 16.7 0.75 V 16.7 50 5 pF 50 50
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CXK77B1840GB
*AC Test Conditions (VDDQ = 1.9V) .... for extended HSTL (for R-L mode only)
(VDD = 3.3V 5%, TA = 0 to 70C) (VDDQ = 1.9V 0.1V, TA = 0 to 70C)
Item Input Reference Voltage Input High Level (Address / Control) Input Low Level (Address / Control) Input High Level (Data) Input Low Level (Data) Input Rise & Fall Time Clock Input Reference Level PECL Input High Voltage PECL Input Low Voltage Input Rise & Fall Time Output Supply Voltage Output Reference Level Output Load Conditions
Conditions VREF = 0.75V VIHCA = 1.25V VILCA = 0.25V VIHD = 1.25V VILD = 0.25V 1V/ns K/K cross 1.45V 0.75V 1V/ns VDDQ = 1.9V 0.95V
Notes
Fig.2 RQ = 250
Fig. 2: AC Test Output Load (VDDQ = 1.9V)
0.95 V 16.7 50 5 pF DQ 16.7 0.95 V 16.7 50 5 pF 50 50
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CXK77B1840GB
Register - Register Mode
Timing Diagram of Read and Deselect Operations
K K
tKHKH tKHKL tKLKH
SA
n
tAVKH tKHAX
n+2
n+3
SW
tWVKH tKHWX
SS
tSVKH tKHSX tGLQV tGLQX
G
tKHQV tKHQX tGHQZ tKHQZ tKHQX1
DQ
Qn-2
Qn-1
Qn
Timing Diagram of Write Operations K K SA SS SW/SBWx G
tDVKH tKHDX
n
n+1
n+2
n+3
DQ
Dn-1
Dn
Dn+1
Dn+2
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CXK77B1840GB
Register - Register Mode
Timing Diagram I of Read-Write-Read Operations (SS Controlled) K K SA SS SW/SBWx G = VIL DQ Read n Qn-1 Deselect Qn
tKHQZ
n
n+2
n+3
n+4
n+5
Dn+2 Write n+2 Read n+3
Qn+3 Read n+4
Timing Diagram II of Read-Write-Read Operations (G Controlled) K K SA SS = VIL SW/SBWx G DQ Read n Qn-1 Dummy Read n n+2 n+3 n+4 n+5
tGHQZ
Qn
Dn+2 Write n+2 Read n+3
Qn+3 Read n+4
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CXK77B1840GB
Register - Latch Mode
Timing Diagram of Read and Deselect Operations
K K
tKHKH tKHKL tKLKH
SA
n
tAVKH tKHAX
n+1
n+3
SW
tWVKH tKHWX
SS
tSVKH tKHSX tKHQV tGLQV tGLQX
G
tKLQV tKLQX tKLQV tKLQX tGHQZ tKHQZ
DQ
Qn-1
Qn
Qn+1
Timing Diagram of Write Operations K K SA SS SW/SBWx G
tDVKH tKHDX
n
n+1
n+2
n+3
DQ
Dn-1
Dn
Dn+1
Dn+2
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CXK77B1840GB
Register - Latch Mode
Timing Diagram of Read-Write-Read Operations K K SA SS SW/SBWx G = VIL DQ Read n
tKHQZ tKHQZ
n
n+1
n+2
n+4
n+5
Qn
Dn+1 Read n+2
Qn+2 Deselect Read n+4
Qn+4
Write n+1
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CXK77B1840GB
Register - Flow Thru Mode
Timing Diagram of Read and Deselect Operations
K K
tKHKH tKHKL tKLKH
SA
n
tAVKH tKHAX
n+1
n+3
SW
tWVKH tKHWX
SS
tSVKH tKHSX tGLQV tGLQX
G
tKHQV tKHQX tGHQZ tKHQZ tKHQX
DQ
Qn-1
Qn
Qn+1
Timing Diagram of Write Operations K K SA SS SW/SBWx G
tDVKH tKHDX
n
n+1
n+2
n+3
DQ
Dn-1
Dn
Dn+1
Dn+2
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CXK77B1840GB
Register - Flow Thru Mode
Timing Diagram of Read-Write-Read Operations K K SA SS SW/SBWx G = VIL DQ Read n
tKHQZ tKHQZ
n
n+1
n+2
n+4
n+5
Qn
Dn+1 Read n+2
Qn+2 Deselect Read n+4
Qn+4
Write n+1
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CXK77B1840GB
Dual Clock Mode
Timing Diagram of Read and Deselect Operations
K K
tKHKH tKHKL tKLKH
SA
n
tAVKH tKHAX
n+1
n+3
SW
tWVKH tKHWX
SS
tSVKH tKHSX
G
tGLQV tKHQV tCHQV tCHQX1 tCHQV tCHQX tGHQZ tGLQX tCHQZ
DQ
tCHKH
Qn-1
tKHCH
Qn
Qn+1
C C
tCHCH tCHCL tCLCH
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CXK77B1840GB
Dual Clock Mode
Timing Diagram of Write Operations K K SA SS SW/SBWx G
tDVKH tKHDX
n
n+1
n+2
n+3
DQ
Dn-1
Dn
Dn+1
Dn+2
Timing Diagram I of Read-Write-Read Operations (SS Controlled) K K SA SS SW/SBWx G = VIL DQ C C Read n Deselect Write n+2 Read n+3 Read n+4 Qn
tCHQZ
n
n+2
n+3
n+4
n+5
Dn+2
Qn+3
Qn+4
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CXK77B1840GB
Dual Clock Mode
Timing Diagram II of Read-Write-Read Operations (G Controlled) K K SA SS = VIL SW/SBWx G DQ C C Read n Dummy Read Write n+2 Read n+3 Read n+4 Qn
***Note*** (1)
n
n+2
n+3
n+4
n+5
tGHQZ
Dn+2
Qn+3
Qn+4
Note 1: In order to prevent glitches on the data bus during write-read operations, when G is driven active (low) following the rising edge of K, the data bus will remain tri-stated until valid data from the most recent read operation is available. Specifically, the data bus will remain tri-stated for the maximum of the following three times: 1.TKHQV 2.TKHCH + TCHQV 3.(K high to G low) + TGLQV
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Test Mode Description
Functional Description
CXK77B1840GB
The CXK77B1840 provides a JTAG boundary scan interface using a limited set of IEEE std. 1149.1 functions. The test mode is intended to provide a mechanism for testing the interconnect between master (processor, controller, etc.), SRAMs, other components and the printed circuit board. In conformance with a subset of IEEE std. 1149.1, the CXK77B1840 contains a TAP controller, Instruction register, Boundary scan register and Bypass register. JTAG Inputs/Outputs are LVTTL compatible only. Test Access Port (TAP) 4 pins as defined in the Pin Description table are used to perform JTAG functions. The TDI input pin is used to scan test data serially into one of three registers (Instruction register, Boundary Scan register and Bypass register). TDO is the output pin used to scan test data serially out. The TDI pin sends the data into LSB of the selected register and the MSB of the selected register feeds the data to TDO. The TMS input pin controls the state transition of 16 state TAP controller as specified in IEEE std. 1149.1. Inputs on TDI and TMS are registered on the rising edge of TCK clock. The output data on TDO is presented on the falling edge of TCK. TDO driver is in active state only when TAP controller is in Shift-IR state or in Shift-DR state. TCK, TMS, TDI must be tied low when JTAG is not used. TAP Controller 16 state controller is implemented as specified in IEEE std. 1149.1. The controller enters reset state in one of two ways: 1. Power up. 2. Apply a logic 1 on TMS input pin on 5 consecutive TCK rising edges. Instruction Register (3 bits) The JTAG Instruction register consists of a shift register stage and parallel output latch. The register is 3 bits wide and is encoded as follow: Octal 0 1 2 3 4 5 6 7
256Kx18, Sync LW, HSTL, rev 4.6
MSB..........LSB 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
Instruction Bypass IDCODE. Read device ID Sample-Z. Sample Inputs and tri-state DQs Bypass Sample. Sample Inputs. Private. Manufacturer use only. Bypass Bypass
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Bypass Register (1 bit)
CXK77B1840GB
The Bypass Register is one bit wide and is connected electrically between TDI and TDO and provides the minimum length serial path between TDI and TDO. ID Registers (32 bits) The ID Register is 32 bits wide and is encoded as follows:
ID[0} Sony ID Part Number Revision Number ID[11:1] ID[27:12] ID[31:28]
1 0000 1110 001 0000 0000 0001 1000 xxxx
Boundary Scan Register (51 bits) The Boundary Scan Registers are 51 bits wide and are listed as follows:
DQ SA SW, SBWx SS, G K, K, C, C ZZ M1, M2 ZQ Place Holder
18 18 3 2 4 1 2 1 2
K/K, C/C inputs are sampled through one differential stage and internally inverted to generate internal K/K, C/C signals for scan registers. Place Holder are required for some NC pins to maintain 51 bits Scan Register for different types of the same family SRAM and for density upgrades. All Place Holder Registers are connected to VSS internally regardless of pin connection externally.
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Scan Order (Order by exit sequence)
CXK77B1840GB
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
3B 3A 3C 2C 2A 1D 2E 2G 1H 3G 4D 4E 4G 4H 4M 2K 1L 2M 1N 2P 3T 2R 4N 2T 3R
SA VSS SA SA SA SA DQb DQb DQb DQb SBWb ZQ SS C C SW DQb DQb DQb DQb DQb SA SA SA SA M1
SA VSS SA SA SA SA DQa DQa DQa DQa DQa G K K SBWa DQa DQa DQa DQa ZZ SA SA SA SA M2
5B 5A 5C 6C 6A 6D 7E 6F 7G 6H 4F 4K 4L 5L 7K 6L 6N 7P 7T 5T 6R 4P 6T 5R
25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
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Ordering Information.
Part Number
CXK77B1840GB
Speed
Register - Register Register - Latch/ Register - Flow Thru 4.8ns Cycle / 4.8ns Access 5.3ns Cycle / 5.3ns Access 5.3ns Cycle / 5.3ns Access 6.5ns Cycle / 6.5ns Access **Dual Clock** 4.0ns Cycle / 5.2ns Access 4.0ns Cycle / 5.2ns Access 4.5ns Cycle / 6.0ns Access 4.5ns Cycle / 6.5ns Access
CXK77B1840GB-4A CXK77B1840GB-4 CXK77B1840GB-45A CXK77B1840GB-45
4.0ns Cycle / 2.3ns Access 4.0ns Cycle / 2.3ns Access 4.0ns Cycle / 2.3ns Access 5.0ns Cycle / 2.5ns Access
Note: Contact Sony Memory Marketing for availability of Dual Clock mode functionality.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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Revision History Rev. # rev 4.0 rev 4.2 Rev. date 8/22/97 11/21/97
CXK77B1840GB
Changes / Modifications to Data-Sheet Initial version, based on TS-2 evaluation Modified AC Electrical Characteristics: R-R Mode: -4.5+ TKHKH -4.5 TGHQZ -4.5 TGHQZ R-L, R-FT Modes: -4 TKHKH -4.5+ TKHQV TGHQZ -4.5 TGHQZ -5 TKHKH DC Mode: -4 TKHQV TKHDX TGLQV TGHQZ -4.5+ TKHQV TGHQZ -4.5 TGHQZ Renamed "-4" bin to "-40" bin in all modes. Renamed "-4.5+" bin to "-45H" bin in all modes. Renamed "-4.5" bin to "-45" bin in all modes. Renamed "-5" bin to "-50" bin in all modes.
5.0ns to 4.5ns 2.5ns to 2.3ns 2.5ns to 2.3ns 5.5ns to 5.0ns 6.5ns to 5.5ns 2.5ns to 2.3ns 2.5ns to 2.3ns 5.5ns to 6.0ns 5.5ns to 5.3ns 1.0ns to 0.8ns 2.3ns to 2.1ns 2.3ns to 2.0ns 6.2ns to 6.0ns 2.5ns to 2.3ns 2.5ns to 2.3ns
Modified DC Recommended Operating Conditions (page-6) VREF + 0.1 to VREF + 0.2 VIH min VIL max VREF - 0.1 to VREF - 0.2 VDIF min 0.2V to 0.4V Added extended HSTL AC Test Conditions (page-12) Provided IDD & ISB typical values (page-7) rev 4.3 01/15/98 Modified AC Electrical Characteristics: Added "-40A" bin to all modes. Deleted "-40" bin from all modes. Deleted "-50" bin from all modes. Renamed "-45H" bin to "-45A" bin in all modes. Modified extended HSTL AC Test Conditions (page-12)
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Rev. # rev 4.4 Rev. date 04/14/98
CXK77B1840GB Changes / Modifications to Data-Sheet Modified AC Electrical Characteristics Deleted "-45" bin from all modes. Renamed "-40A" bin to "-4A" bin in all modes. R-R Mode: -4A TKHKH 4.5ns to 4.0ns -45A TKHKH 4.5ns to 4.0ns TKHQV 2.5ns to 2.3ns TKHQZ 2.5ns to 2.3ns TGLQV 2.5ns to 2.3ns R-L, R-FT Modes: Added "R-FT timing parameters guaranteed by design only" note for all bins. Removed TKHQZ1 from all bins. -4A TGHQZ 2.3ns to 2.2ns DC Mode: Added "DC operation not functionally verified" note for all bins. Removed TKHQX and TKHQX1 from all bins. -4A TKHQV 5.3ns to 5.2ns Modified DC Recommended Operating Conditions (page-6) RQ min 200 to 175 Modified DC Electrical Characteristics (page-7) ROUT min (RQ/5)*0.9 to (RQ/5)*0.925 (RQ/5)*1.1 to (RQ/5)*1.075 ROUT max Updated all timing diagrams (page-13 through page-21). Added "Contact Sony Memory Marketing for DC model availability" note (page-1 and page-25). Removed "Preliminary" from the data sheet
rev 4.5
08/12/98
Modified AC Electrical Characteristics R-L, R-FT Modes: -4A TKHKH TKHQV -45A TKHKH TKHQV Modified AC Electrical Characteristics Added "-4" bin to all modes. Added "-45" bin to all modes.
5.0ns to 4.8ns 5.0ns to 4.8ns 5.5ns to 5.3ns 5.5ns to 5.3ns
rev 4.6
08/20/98
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